The subject matter disclosed herein relates to solutions for modeling objects in the design of integrated circuits. More specifically, the subject matter disclosed herein relates to developing a library device and generating an on-chip model for open termination fringe capacitance in an integrated circuit and an associated design structure.
As integrated circuit technologies shrink in size along with the advancement in technology, interconnect wiring effects can impact the performance of those integrated circuits significantly. Generating accurate and workable models of the wires (e.g., interconnect lines, vias, etc.) can aid in effectively designing the integrated circuit to avoid negative effects such as unwanted fringe capacitances between wires, or account for these effects in advance.
Conventional approaches for evaluating and modeling these negative effects (e.g., fringe capacitances) use parasitic extraction tools after the integrated circuit layout has been designed. However, these late-stage (post-layout) approaches fail to generate models that effectively compensate for the effects of fringe capacitances at pre-layout stage.